1. Field of the Invention
The present invention relates to the field of digital data processing and, in particular, to a method and apparatus for performing signed/unsigned multiplication.
2. Background Information
The demand for higher performance multimedia applications has prompted the development of faster, more powerful processors that consume less power, and take up less space on a printed circuit board, leaving room for additional feature enhancements. Multiplication is one of the most common, basic tasks needed for computational purposes. Those skilled in the art will appreciate that nearly all multimedia applications such as digital signal processing (DSP), digital filtering, graphics, audio and video rendering require fast, area efficient multipliers. Due to the frequency of multiplication computations, multipliers are not only located within central processing units (CPU) or math co-processors, but in nearly any controller embedded within any digital system. Those skilled in the art will appreciate that unsigned multiplication is performed on numbers represented in floating point format, whereas integer multiplication is performed in a signed, 2""s-complement format. Consequently, prior art controllers have typically relied on separate multiplier circuitry, one each for signed and unsigned multiplication.
Simplistically, unsigned multiplication is performed in a controller in much the same way that we learned in elementary school. That is, a multiplicand is multiplied by each digit in the multiplier to create a corresponding number of rows of partial products, which are then summed to produce the final product. Within a controller, multiplication is performed with a series of logic gates, wherein the multiplicand is ANDed with each bit of the multiplier to produce rows of partial products. A number of hierarchically arranged carry-save adders (CSA""s) compress the partial products which are then summed to produce the final product. Signed multiplication, however, adds a level of complexity as the sign of each of the multiplicand and multiplier is embedded within the number itself and must be properly carried through the calculation in the partial products. A number of methods have been proposed which deal with the embedded signs inherent in signed multiplication, with the most popular of such methods being Booth""s algorithm. A complete description of Booths algorithm can be found, for example, in Hennessy, et al., Computer Architecture: A Quantitative Approach, Second Edition, Appendix A: Computer Arithmetic by D. Goldberg, Morgan Kaufman Publishers, San Mateo, Calif., 1996.
Architecturally, a number of alternative multiplier designs exist. Those skilled in the art will appreciate that each of the architecturally unique multipliers have been developed with the goal of decreasing the amount of time (measured in clock cycles) necessary to complete multiplication tasks. Those skilled in the art will appreciate, however, that prior art multiplier circuitry is generally quite large, requiring a large amount of die space on the controller. While some of the prior art solutions for increasing the speed of multiplication may have had a collateral effect of reducing the amount of space consumed by the multiplier circuitry, e.g., the Wallace tree architecture, those skilled in the art will appreciate that such space savings were nominal, at best.
Thus, a method and apparatus for performing signed/unsigned multiplication is required that overcomes the inherent limitations and deficiencies commonly associated with the prior art. Just such a method and apparatus is presented in accordance with the teachings of the present invention that achieves these and other desired results.
In accordance with the teachings of the present invention, a method and apparatus for performing signed and unsigned multiplication is presented. In particular, in accordance with a first embodiment of the present invention, an apparatus is presented comprising a computation cell to generate a plurality of product terms, a compressor, coupled to the computation cell, and a selector coupled to each of the computation cell and the compressor. The selector, couples one output of the computation cell to an input of the compressor, and selects whether the compressor receives the partial product term from the compressor or an inverse thereof. The compressor is used to generate a pair of product terms from the received plurality of product terms.